JFET Roulette

The schematic
A very peculiar voltage follower

So what's going on here?

Well, when I was first properly learning about JFETs, our lecturer emphasized how the parameter spread is really bad. That's when I got the idea for this circuit. So what does it do? It's a simple source follower, Q1 acts as the follower and Q2 acts as a current source. If the devices are matched (think identical), the current sinked by Q2 with zero gate-source voltage is gonna be the same as what Q1 sources with the same zero gate-source voltage, so there will be no voltage shift between the input and the output - nice. Apparently, it used to be used in oscilloscopes because of that, hence the name ('scope follower). What's more, since the JFETs are the same, their temperature coefficient is also the same, so the circuit will be quite immune to temperature drift. Now, even with matched JFETs (either hand-matched discretes or, much better because of temperature coupling, two JFETs on a single die), you'd usually add some resistors to bring the current down from I_DSS, like this:
The (better) schematic
Better source follower

It's the same idea, but some voltage has to drop on R3, so the gate-source voltage of Q2 will become negative and the current will go down below I_DSS. Since R2=R3 and Q1 will still be sourcing as much as Q2 is sinking, the input-output voltage shift is still zero. Ok, but why? Well, for one, trimming R3 makes getting true zero input-output voltage shift possible even with non-identical (i.e. real) JFETs. Even more importantly, the parasitic gate-source capacitance of Q1 (aka the follower's input capacitance) goes down when its gate-source voltage is decreased (search for 'junction capacitance' if you're interested why).

Still, what about the roulette?

Well, operating with currents close to I_DSS is beneficial, because it gets you higher transconductance (which is the same as lower output impedance). Now, remember that infamous parameter spread? If you just slap on two random JFETs, even from the same tape (or reel, if you're living that sweet XXI century life), I_DSS of Q2 may be waaaay higher than I_DSS of Q1, things might heat up and your source follower may decide to release its magic smoke. So the circuit I came up with is more of a little inside joke instead of anything practical, still, you just might get yourself a crazy-unstable low-output-impedance voltage follower. You will lose the zero voltage shift though, so really, there's no point.

Ok, but will it blow?

Gee, I hope so.
But for real, I've been putting off writing this page for so long (almost a year) because I thought there would be an opportunity to sneak on a couple of dozens of JFETs to my next lcsc or mouser or whatever order, but the opportunity still hasn't come up. I would just buy a bunch of JFETs locally, but that is not... economically viable. So, until then, let's just look at what LTSpice has to say.

SPICE'ing the day away

There's no thermal runaway in LTSpice, even worse, there's no production parameter spread in LTSpice, but we'll just go around that by using J111 as Q2 and J113 as Q1 (J111-113 are binned devices of the same type).
The SPICE schematic
LTSpice schematic (click for download)

We can check the calculated power dissipation by just hovering the mouse cursor over an element. Let's check J2:
J2 power dissipation

Great, only 84mW, well within spec. Ok, what about J1?
J1 power dissipation

Aaaaand it's fired, over 1W of dissipated power exceeds both 625mW of the THT-packaged J113 and 350mW of its SMD counterpart (MMBFJ113).


Be aware of parameter spread and always mark any special requirements (like the need for matched devices) on schematics.

I'll update this page with experimental data if I ever get around to gathering any, ~Filip Piórski, 2021-01-07